This application claims the benefit of Korean Patent Application No. 2001-1019, filed Jan. 8, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
The present invention relates to memory devices, and more particularly to multi-chip memory devices that include at least two chips in one package, memory modules including the multi-chip memory devices, and control methods for the multi-chip memory devices and memory modules.
Integrated circuit memory chips are widely used in consumer and commercial applications. In these applications, it may be desirable to increase the amount of memory that can be packaged in a given area or volume. Accordingly, multi-chip memory devices have been used, wherein at least two integrated circuit memory chips are encapsulated in a common package that includes a plurality of external terminals. It is also known to mount a plurality of multi-chip memory devices on first and second opposing surfaces of a memory module substrate, to provide a memory module.
For example, a 144-pin/200-pin memory module mounted on a main board of a notebook computer can include a small outline dual in-line memory module (SODIMM) having a width of 1.25 inches, a height of 2.66 inches and a thickness of 0.15 inches and a micro-dual in-line memory module (xcexc-DIMM) having a width of 1.18 inches, a height of 1.5 inches and a thickness of 0.15 inches. The size of the memory module is determined in accordance with the joint electronic devices engineering council (JEDEC) standard. On such a memory module, up to four synchronous dynamic random access memory (SDRAM) of a 54-pin thin small outline package (TSOP) type can be mounted on both its front surface and its rear surface, respectively.
FIGS. 1A and 1B are plan views illustrating, respectively, configurations of a front surface and a rear surface of a conventional 144-pin/200-pin memory module. As shown in FIGS. 1A and 1B, the front surface 10 of the module includes four memory devices 12-1 to 12-4, and the rear surface 20 also includes four memory devices 22-1 to 22-4. On both the front and rear surfaces 10 and 20 of the memory module, signal lines are arranged to connect the memory devices 12-1 to 12-4 and 221 to 22-4 with connecting pins 14-1, 14-2, 24-1, and 24-2. The connecting pins 14-1 and 14-2 of the front surface 10 and the connecting pins 24-1 and 24-2 of the rear surface 20 are connected with signal lines of a main board or motherboard through slots of the main board. A pin configuration of the memory module includes 12 input pins, 2 bank selecting signal pins, 64 data input/output pins, one row address strobe pin, one column address strobe pin, one write enable signal pin, 8 data input/output mask pins, and a predetermined number of no-connection pins.
FIG. 2 is a cross-sectional view of an SDRAM of the TSOP type for mounting on the module shown in FIG. 1. As shown in FIG. 2, the memory device includes an encapsulating package 30, a chip 32, lead frames 34-1 and 34-2, pads 361 and 36-2, insulating materials 38-1 and 38-2, and bonding wires 40-1 and 40-2. The chip 32 and the lead frames 34-1 and 34-2 are respectively insulated by the insulating materials 38-1 and 38-2, and the lead frames 34-1 and 34-2 and the pads 36-1 and 362 are respectively connected with each other via the bonding wires 40-1 and 40-2. The lead frames 34-1 and 34-2 are used as signal input/output pins.
FIG. 3 is a plan view illustrating a pin configuration of an SDRAM of the 54-pin TSOP type. Pin numbers 1, 14 and 27 denote a power supply (VDD) pin. Pin numbers 28, 41 and 54 denote a power supply ground pin. Pin numbers 3, 9, 43 and 49 denote data output power pins. Pin numbers 6, 12, 46 and 52 denote data output power ground pins. Pin number 16 denotes a write enable signal (WEB) applying pin. Pin number 17 denotes a column address strobe signal (CASB) applying pin. Pin number 18 denotes a row address strobe signal (CASB) applying pin. Pin number 19 denotes a chip select signal (CSB) applying pin. Pin numbers 20 and 21 denote bank select address (BA0, BA1) applying pins. Pin numbers 22 to 26 and 29 to 36 denote address (A0 to A12) applying pins. Pin number 37 denotes a clock enable signal (CKE) applying pin. Pin number 38 denotes a system clock signal (CLK) applying pin. Pin numbers 15 and 39 denote data input/output mask signal (LDQM, UDQM) applying pins. Pin numbers 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51 and 53 denote data chip/output signal (DQ0 to DQ15) pins. Pin number 40 denotes a no-connection pin.
A chip select signal (CSB) applied to the chip select signal (CSB) applying pin enables inputting of signals inputted to all the pins described above except the system clock signal (CLK) applying pin, the clock enable signal (CKE) applying pin and the data input/output mask signal (LDQM, UDQM) applying pins, so that an operation of the memory device is enabled. The system clock signal (CLK) applying pin is a pin for inputting the clock signal applied from a controller of the main board. Particularly, the clock enable signal (CKE) applying pin may be used as a control signal applying pin for a power-down mode of the notebook computer.
FIG. 4 is a plan view illustrating the memory devices mounted on the memory module of FIG. 1 and control signal lines. The memory module of FIG. 4 is 256M byte memory module on which eight memory devices 12-1 to 12-4 and 22-1 to 22-4 of 16Mxc3x9716 bits are mounted. In FIGS. 1 and 4, like reference numerals denote like parts.
The memory devices 12-1 to 12-4 arranged in a dotted line portion 10xe2x80x2 are the memory devices mounted on the front surface 10 of the memory module. An operation of the memory devices 12-1 to 12-4 is enabled in response to the chip select signal (CSB0), and the system clock signal (CLK0) is enabled in response to the clock enable signal (CKE0), so that data is input or output in response to the system clock signal (CLK0). Data of 16 bits is input into or output from each of the memory devices 12-1 to 12-4, and therefore the total data input into or output from the memory devices 12-1 to 12-4 is 64 bits.
The memory devices 22-1 to 22-4 arranged in a dotted line portion 20xe2x80x2 are the memory devices mounted on the rear surface 20 of the memory module. An operation of the memory devices 22-1 to 22-4 is enabled in response to the chip select signal (CSB1), and the system clock signal (CLK1) is enabled in response to the clock enable signal (CKE1), so that data is input or output in response to the system clock signal (CLK1). Data of 16 bits is input into or output from each of the memory devices 22-1 to 22-4, and therefore the total data input into or output from the memory devices 22-1 to 22-4 is 64 bits.
Other signal lines, which are not shown in FIG. 4, are connected to each other via common signal lines. That is, as shown in FIG. 4, in the 256M byte memory module, four memory devices of 16Mxc3x9716 bits are respectively mounted on both its front surface 10 and its rear surface 20. The four memory devices arranged on the front surface 10 and the four memory devices arranged on rear surface 20 can be operated independent from each other in order to input/output data of 64 bits into/from the 256M byte memory module. As shown in FIG. 4, in case the four memory devices mounted on the front and rear surfaces 10 and 20 are separately operated, in order to increase a capacity of the memory module, it may be desirable to increase the capacity of the memory devices. For example, in order to configure a 512M byte memory module, four memory devices of 16Mxc3x9716 bits may respectively be mounted on both the front and rear surfaces of the memory module. However, these high capacity memory modules may be difficult to manufacture. Also, when the memory devices are operated as shown in FIG. 4, it may be difficult to configure a memory module having a large capacity using the memory devices having a small capacity.
In efforts to overcome these and/or other potential problems, four memory devices, which are configured such that two TSOP packages of 32Mxc3x978 bits are stacked, are mounted on both the front surface 10 and the rear surfaces 20, so that the memory module may have a capacity of 512M byte. However, since the memory module is configured in such a way that two packages are stacked, the memory device may become too thick.
In efforts to overcome these and/or other potential problems, a memory module that packages two chips into one package has been introduced. FIG. 5 is a cross-sectional view of a multi-chip memory device wherein two chips are encapsulated into one package. As shown in FIG. 5, the multi-chip memory device includes upper and lower chips 52-1 and 52-2 disposed to be opposite to each other and a common package 50 that encapsulates the upper and lower chips 52-1 and 52-2. The upper chip 52-1 includes first and second lead frames 54-1 and 54-2, first and second insulating materials 56-1 and 56-2, first and second pads 58-1 and 58-2, and first and second bonding wires 60-1 and 60-2. The lower chip 52-2 includes first and second lead frames 54-3 and 54-4, first and second insulating materials 56-3 and 56-4, first and second pads 58-3 and 58-4, and first and second bonding wires 60-3 and 604. 4.
In the multi-chip memory device of FIG. 5, the first lead frame 54-1 of the upper chip 52-1 and the first lead frame 54-3 of the lower chip 52-2 are connected to each other, and the second lead frame 54-3 of the upper chip 52-1 and the second lead frame 54-4 of the lower chip 52-2 are also connected to each other. The lead frames 54-1 to 54-4 are connected to a plurality of control signal applying pins of the upper and lower chips 52-1 and 52-2, respectively. The lead frames connected to a plurality of data input/output pins of the chips 52-1 and 52-2 are not connected to each other and are configured independent of each other. In other words, all first and second lead frames of the chips 52-1 and 52-2 except the lead frames connected to the data input/output pins of the chips 52-1 and 52-2 of 32Mxc3x978 bits are connected to each other, respectively. As a result, the multi-chip memory device has the same pin configuration as shown in FIG. 3. The first and second lead frames 54-1 and 54-2 of FIG. 5 are used as signal input/output pins.
FIG. 6 is a plan view illustrating a pin configuration of the SDRAM of a 54-pin TSOP type of 32Mxc3x978 bits. In FIG. 6, pin numbers 4, 7, 10, 15, 40, 42, 45, 48, and 51 denote a no-connection (NC) pin. In case of a multi-chip memory device wherein the two chips 52-1 and 52-2 are not packed into one package, the no-connection lead frames of the chip 52-1 may be connected with the data input/output (DQ0 to DQ7) lead frames of the chip 52-2. Therefore, the memory device can have the same pin configuration as shown in FIG. 3 and becomes an SDRAM of 32Mxc3x978 bitsxc3x972.
In the memory device of FIG. 5, the two chips 52-1 and 52-2 are simultaneously enabled in response to the chip select signal, and the system clock signal is enabled in response to the clock enable signal, so that data of 8 bits is input into or output from each of the two chips 52-1 and 52-2 in response to the system clock signal. However, since the two chips perform an input/output of data at the same time, excessive heat may be generated, whereby performance of the memory device may be reduced.
FIG. 7 is a plan view illustrating the memory devices of FIG. 5 mounted on the memory module of FIG. 1 and control signal lines on the main board. The memory module of FIG. 7 includes eight memory devices 12-1 to 12-4 and 22-1 to 224 of 32Mxc3x978 bitsxc3x972 and thus has a capacity of 512M bytes. In FIGS. 1 and 7, like reference numbers denote like parts.
The memory devices 12-1 to 12-4 arranged in a dotted line portion 10xe2x80x2 are mounted on the front surface 10 of the memory module. Operation of the memory devices 12-1 and 12-2 is enabled in response to the chip select signal (CSB0), and the system clock signal (CLK0) is enabled in response to the clock enable signal (CKE0), so that data of 32 bits is input or output in response to the system clock signal (CLK0). Also, operation of the memory devices 12-3 and 12-4 is enabled in response to the chip select signal (CSB0), and the system clock signal (CLK1) is enabled in response to the clock enable signal (CKE0), so that data of 32 bits is input or output in response to the system clock signal (CLK1). That is, the memory devices 12-1 to 12-4 are enabled in response to the chip select signal (CSB0) and the clock enable signal (CKE0) and input or output data of 64 bits in response to the system clock signal (CLK0, CLK1).
The memory devices 22-1 to 22-4 arranged in a dotted line portion 20xe2x80x2 are mounted on the rear surface 20 of the memory module. Operation of the memory devices 22-1 and 22-2 is enabled in response to the chi select signal (CSB1), and the system clock signal (CLK0) is enabled in response to the clock enable signal (CKE1), so that data of 32 bits is input or output in response to the system clock signal (CLK0). Also, operation of the memory devices 22-3 and 22-4 are enabled in response to the chip select signal (CSB1), and the system clock signal (CLK1) is enabled in response to the clock enable signal (CKE1), so that data of 32 bits input or output in response to the system clock signal (CLK1). That is, the memory devices 22-1 to 22-4 are enabled in response to the chip select signal (CSB1) and the clock enable signal (CKE1) and input or output data of 64 bits in response to the system clock signal (CLK0, CLK1).
However, as described above, conventional memory devices may have degraded performance due to heat that may be generated when the two chips perform an input/output of data at the same time.
Embodiments of the present invention provide multi-chip memory devices that include at least two integrated circuit memory chips, each of which includes a plurality of corresponding address pads, data pads and control signal pads, and a common package that encapsulates the at least two integrated circuit memory chips, and that includes a plurality of external terminals. An internal connection circuit in the common package is configured to connect at least one of the corresponding control signal pads of each of the integrated circuit memory chips to separate ones of the plurality of external terminals, to allow independent external control of each of the integrated circuit memory chips that are encapsulated in the common package. By allowing independent external control, the at least two integrated circuit memory chips may not be operated simultaneously. Accordingly, embodiments of the internal connection circuit in the common package can provide means for independently controlling each of the integrated circuit memory chips that are encapsulated in the common package, via at least one of the plurality of external terminals. Generation of heat in the multi-chip memory package therefore may be reduced.
In some embodiments, the at least two integrated circuit memory chips comprise at least two identical integrated circuit memory chips. In other embodiments, the at least one of the corresponding control circuit pads comprises a chip select signal pad, and the internal connection circuit in the common package is configured to connect the chip select signal pad of each of the integrated circuit memory chips to separate ones of the plurality of external terminals, to allow external chip selection of each of the integrated circuit memory chips that are encapsulated in the common package. In other embodiments, the at least one of the corresponding control circuit pads comprises a clock enable signal pad, and the internal connection circuit in the common package is configured to connect the clock enable signal pad of each of the integrated circuit memory chips to separate ones of the plurality of external terminals, to allow independent external clocking of each of the integrated circuit memory chips that are encapsulated in the common package. In yet other embodiments, the internal connection circuit is further configured to connect the corresponding data pads of each of the integrated circuit memory chips in common to a plurality of corresponding external terminals. In still other embodiments, the internal connection circuit is configured to connect the corresponding data pads of the integrated circuit memory chips to separate ones of the external terminals.
Multi-chip memory devices, according to any of the embodiments that were described above, may be combined to form memory modules according to embodiments of the invention. The memory modules include a memory module substrate having first and second opposing surfaces. At least one multi-chip memory device, as described above, is provided on the first surface and on the second surface.
In some embodiments of memory modules, the memory module substrate further comprises an external connection circuit that is configured to simultaneously enable only one of the at least two integrated circuit chips in each of the at least one multi-chip memory device on the first surface and on the second surface. In other embodiments, the external connection circuit is further configured to simultaneously enable only a corresponding one of the at least two integrated circuit chips in each of the at least one multi-chip memory device on the first surface and on the second surface. In yet other embodiments, the external connection circuit is further configured to simultaneously enable only a first of the at least two integrated circuit chips in each of at least one multi-chip memory device on the first surface, and to simultaneously enable only a second of the at least two integrated circuit chips in each of the at least one multi-chip memory device on the second surface. In still other embodiments, the external connection circuit is further configured to simultaneously enable only a first of the at least two integrated circuit chips in each of the at least one multi-chip memory devices on a first portion of the first surface and on a corresponding first portion of the second surface, and to simultaneously enable only a second of the at least two integrated circuit chips in each of the at least multi-chip memory devices on a second portion of the first surface and on a corresponding second portion of the second surface.
In other embodiments, the external connection circuit further comprises a first external system clock circuit that is configured to provide a first external system clock to the at least two integrated circuit memory chips in each of the at least one multi-chip memory device on the first surface and to provide a second external system clock signal to the at least two integrated circuit memory chips in each of the at least one multi-chip memory devices on the second surface. In yet other embodiments, the external connection circuit further comprises a first external system clock circuit that is configured to provide a first external system clock signal to the at least two integrated circuit memory chips in each of the at least one multi-chip memory devices on a first portion of the first surface and on a corresponding first portion of the second surface, and to provide a second external system clock signal to the at least two integrated circuit memory chips in each of the at least one multi-chip memory devices on a second portion of the first surface and on a corresponding second portion of the second surface.
According to method embodiments of the present invention, a multi-chip module device that comprises at least two integrated circuit memory chips and a common package that encapsulates the at least two integrated circuit memory chips and that includes a plurality of external terminals, is controlled by independently controlling each of the integrated circuit memory chips that are encapsulated in the common package, from external of the common package. Independent control may be provided, according to embodiments of the present invention, by independently selecting each of the integrated circuit memory chips that are encapsulated in the common package and/or by independently enabling a clock signal for each of the integrated circuit memory chips that are encapsulated in the common package.
According to other method embodiments, a memory module that includes a memory module substrate and at least one multi-chip memory device on the first surface and on the second surface thereof, is controlled by simultaneously enabling only one of the at least two integrated circuit memory chips in each of the at least one multi-chip memory devices on the first surface and on the second surface.